1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor.
2. Description of the Related Art
In order to achieve more rapid operation of a field effect transistor, technological developments such as providing a very short gate length of the field effect transistor, providing a shallow source/drain region and the like are proceeded. Such technologies includes a technology described in Japanese Patent Laid-Open No. 2004-253,446.
Japanese Patent Laid-Open No. 2004-253,446 points out a fact that, in the process for manufacturing a metal oxide semiconductor (MOS) transistor, a redistribution is occurred as a diffusion of an implanted impurity is occurred during an annealing process after an ion implantation process, and therefore a dispersion of the impurity due to the redistribution of ions should be of achieving the considerably reduced gate length and/or providing the shallow source drain. It is also described that a transient enhanced diffusion (TED) becomes a problem in recent years as a factor for causing the redistribution corresponding to the diffusion of the implanted impurity, and that the TED is caused by a point defect created in the semiconductor substrate during the ion implantation process and is a phenomena, in which a redistribution of the impurity is occurred at a relatively lower temperature.
According to Japanese, Patent Laid-Open No. 2004-253,446, it is described that a MOS transistor is obtained, which provides smaller variation of impurity profile in the source/drain region caused by a heat treatment in the process for forming side wall films of a gate electrode and involves inhibiting a diffusion of an impurity caused by the TED and the corresponding short-channel effect, by establishing an annealing temperature in consideration of a re-diffusion length characteristic for the impurity over the annealing temperature after the ion implantation process and by determining a sequential order of the ion implantation processes.
In addition, Japanese Patent Laid-Open No. 2004-63,574 describes the following approaches for providing a method for manufacturing a MOS transistor. According to Japanese Patent Laid-Open No. 2004-63,574, in the process for forming extension regions of the source/drain, after forming the shallow impurity ion-implanted region on a surface layer of a Si substrate, an annealing process is conducted in order to activate impurity ions in an impurity ion-implanted region. A flash lamp annealing process, which employs a flashlamp and is conducted at higher temperature with a short duration time, is described as an exemplary process of such type of annealing process.
It is also described that, when the source/drain region is formed, a two-step annealing process is conducted after a deep impurity-implanted region is formed in a surface layer of the Si substrate. First, a first heat treatment (pre annealing) is conducted via a rapid thermal annealing (RTA) employing a halogen lamp. Successively, a second thermal process is conducted by employing a Xe flashlamp. Such second heat treatment is a flash lamp annealing for activating an impurity-diffusing region.